Eric S. Fetzer is an Intel Fellow in charge of Technology Alignment and Pathfinding in the Design Engineering Group. Eric is responsible for product process co-optimization and pathfinding solutions at the intersection of design, process, architecture and test. Prior to assuming his current role in 2017, Fetzer led design convergence efforts on Intel Atom Microservers, and drove circuit design methodology on Intel Xeon Processors. Earlier in his Intel career, he was responsible for various aspects of the design, convergence and delivery of Intel Xeon and Intel® Itanium® processors. Before joining Intel in 2005, Eric held design engineering positions at Hewlett Packard Enterprise, and IBM. Fetzer earned a bachelor’s degree in electrical and computer engineering from the University of Wisconsin – Madison. His work in the areas of circuit design, memories, SOC clocking, and power management has led to sixteen U.S. patents and over a dozen publications.